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Microchip Technology APA075-TQG144I Datasheet

Maximum performance numbers in this datasheet are based on characterized data. Actel does not guaranteeperformance beyond the limits specified within the datasheet.

Features and Benefits:

High Capacity

Commercial and Industrial

• 75,000 to 1 Million System Gates

• 27 K to 198 Kbits of Two-Port SRAM

• 66 to 712 User I/Os

Military

• 300, 000 to 1 Million System Gates

• 72 K to 198 Kbits of Two Port SRAM

• 158 to 712 User I/Os

Reprogrammable Flash Technology

• 0.22 µm 4 LM Flash-Based CMOS Process

• Live At Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• No Configuration Device Required

• Retains Programmed Design during Power-Down/Up Cycles

• Mil/Aero Devices Operate over Full Military Temperature Range

Performance

• 3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over militarytemperature)

• Two Integrated PLLs

• External System Performance up to 150 MHz

Secure Programming

• The Industry’s Most Effective Security Key (FlashLock®)

Low Power

• Low Impedance Flash Switches

• Segmented Hierarchical Routing Structure

• Small, Efficient, Configurable (Combinatorial or Sequential)Logic Cells

High Performance Routing Hierarchy

• Ultra-Fast Local and Long-Line Network

• High-Speed Very Long-Line Network

• High-Performance, Low Skew, Splittable Global Network

• 100% Routability and UtilizationI/O

• Schmitt-Trigger Option on Every Input

• 2.5 V / 3.3 V Support with Individually-Selectable Voltageand Slew Rate

• Bidirectional Global I/Os

• Compliance with PCI Specification Revision 2.2

• Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant

• Pin-Compatible Packages across the ProASICPLUS FamilyUnique Clock Conditioning Circuitry

• PLL with Flexible Phase, Multiply/Divide, and DelayCapabilities

• Internal and/or External Dynamic PLL Configuration

• Two LVPECL Differential Pairs for Clock or Data InputsStandard FPGA and ASIC Design Flow

• Flexibility with Choice of Industry-Standard Front-End Tools

• Efficient Design through Front-End Timing and GateOptimizationISP Support

• In-System Programming (ISP) via JTAG PortSRAMs and FIFOs

• SmartGen Netlist Generation Ensures Optimal Usage ofEmbedded Memory Blocks

• 24 SRAM and FIFO Configurations with Synchronous andAsynchronous Operation up to 150 MHz (typical)


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