Features:

This datasheet is for LPDDR4 and LPDDR4X unified product based on LPDDR4X information. Refer to LPDDR4 setting section LPDDR4 1.10V VDDQ at the end of this datasheet.

• Ultra-low-voltage core and I/O power supplies

– VDD1 = 1.70–1.95V; 1.80V nominal

– VDD2 = 1.06–1.17V; 1.10V nominal

– VDDQ = 1.06–1.17V; 1.10V nominal

or Low VDDQ = 0.57–0.65V; 0.60V nominal

• Frequency range

– 2133–10 MHz (data rate range: 4266–20 Mb/s/pin)

• 16n prefetch DDR architecture

• 8 internal banks per channel for concurrent operation

• Single-data-rate CMD/ADR entry

• Bidirectional/differential data strobe per byte lane

• Programmable READ and WRITE latencies (RL/WL)

• Programmable and on-the-fly burst lengths (BL =16, 32)

• Directed per-bank refresh for concurrent bank operation and ease of command scheduling

• Up to 8.5 GB/s per die

• On-chip temperature sensor to control self refresh rate

• Partial-array self refresh (PASR)

• Selectable output drive strength (DS)

• Clock-stop capability

• RoHS-compliant, “green” packaging

• Programmable VSS (ODT) termination

Options Marking:

• VDD1/VDD2/VDDQ: 1.80V/1.10V/1.10V or 0.60V D

• Array configuration

– 512 Meg × 32 (2 channels ×16 I/O) 512M32

– 1024 Meg × 32 (2 channels ×16 I/O) 1024M32

• Device configuration

– 512M16 × 2 die in package D2

– 512M16 × 4 die in package D4

• FBGA “green” package

– 200-ball WFBGA (10mm × 14.5mm ×0.8mm, Ø0.35 SMD) DS

– 200-ball VFBGA (10mm × 14.5mm ×0.95mm, Ø0.35 SMD) DT

• Speed grade, cycle time

– 535ps @ RL = 32/36 -053

– 468ps @ RL = 36/40 -046

• Operating temperature range

– –25°C to +85°C WT

• Revision