General Description:

The only reprogrammable and highest density radiation-hardened (RH) FPGA, the space-grade Virtex®-5QV FPGA provides RH by design technology to meet the requirements of space applications that demand high-performance as well as high reliability. For years, ASICs were the only solution available to system designers of high-performance space applications with long development and fabrication times as well as high non-recurring engineering (NRE) costs. The Virtex-5QV FPGA combines unparalleled density, performance, and radiation hardening with the flexibility of reconfigurability without the high risk of ASICs.The Virtex-5QV device provides the compelling set of performance, features, and solutions for the radiation-hardened systems market. Using the second generation Advanced Silicon Modular Block (ASMBL™) column-based architecture, the Virtex-5QV FPGA contains an array of features to address the needs of a wide variety of advanced logic designs and many dedicated system-level blocks, including powerful 36 Kb block RAM and FIFOs, second-generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally controlled impedance, ChipSync™ source-synchronous interface blocks, enhanced clock management tiles with integrated digital clock managers (DCMs), phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional features include power-optimized, high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, and tri-mode Ethernet Media Access Controllers (MACs). These features allow advanced logic designers to build the highest levels of connectivity and performance into their FPGA-based systems. Built on a proven 65-nm copper process technology, the Virtex-5QV FPGA is a modern programmable alternative to custom ASIC technology. The Virtex-5QV FPGA offers the latest solution for addressing the needs of critical space missions where design changes can be accommodated late in the program or through reprogrammability, even after launch.A Virtex-5QV FPGA provides exceptional hardness to single-event upsets (SEUs), total immunity to single-event latch-ups (SELs),total ionizing doses (TIDs) of over 1 Mrad(Si), and datapath protection from single-event transients (SETs). Compatibility with the commercial and defense-grade Virtex-5 FPGAs allows for low-cost, rapid prototyping and easy design migration to flight hardware without the need for PCB changes.

Summary of Radiation-Hardened Virtex-5QV Device Features:

• The only reprogrammable RH FPGA in the industry

• Highest density RH FPGA

• Product intended for use in Space environment offered in full V-Grade and B-Grade manufacturing and screening 

process flows

• The product grades are differentiated via the test flow process only

• High signal-integrity ceramic flip-chip column grid array packaging

• Best-in-class signal and power integrity performance levels achieved with chip capacitors mounted onto the FPGA 

substrate connected to the VCCINT, VCCAUX, and VCCO power supply rails

• The same package substrate and chip capacitors are used in the assembly of the B-Grade and V-Grade products.

• Guaranteed operation over full military temperature range (–55°C to +125°C)

• Guaranteed 1 Mrad(Si) total ionizing dose per method 1019

• Guaranteed SEE latch-up immunity to LET >100 MeV per mg-cm2

• Radiation-Hardened By Design (RHBD) technology

• SEU Hardened Configuration Memory Cells and control logic

• Configuration Memory Orbital Upset Rate (GEO): 3.8E-10 errors/bit/day

• Configuration Control Logic Single-Event Functional Interrupt (SEFI) Orbital Upset Frequency (GEO): less than 

once every 10,000 years

• SEU and SET Hardened CLB flip-flops

• SEU Hardened IOB flip-flops and DCI control

• Embedded error detection and correction (EDAC) and autonomous writeback for high-performance Block Memory SEU 

Mitigation

• Fully characterized for space radiation effects in heavy ion and proton environments

• Most advanced, high-performance, optimal-utilization, FPGA logic

• Real 6-input look-up table (LUT) technology

• Dual 5-LUT option

• Improved reduced-hop routing

• 64-bit distributed RAM option

• SRL32/Dual SRL16 option

• Powerful clock management tile (CMT) clocking

• Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting

• PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division

• 36 Kb block RAM/FIFOs

• True dual-port RAM blocks

• Enhanced optional programmable FIFO logic

• Programmable

- True dual-port widths up to x36

- Simple dual-port widths up to x72

• Built-in optional error-correction circuitry

• Optionally program each block as two independent 18 Kb blocks

• High-performance parallel SelectIO technology

• 1.2 to 3.3V I/O operation

• Source-synchronous interfacing using ChipSync technology

• Digitally controlled impedance (DCI) active termination

• Flexible fine-grained I/O banking

• High-speed memory interface support

• Advanced DSP48E slices

• 25 x 18, twos complement, multiplication

• Optional adder, subtracter, and accumulator

• Optional pipelining

• Optional bitwise logical functionality

• Dedicated cascade connections

• Flexible configuration options

• SPI and Parallel flash interface

• Multi-bitstream support with dedicated fallback reconfiguration logic

• Auto bus width detection capability

• Off-chip thermal monitoring capability

• Integrated Endpoint blocks for PCI Express

• Compliant with the PCI Express Base Specification v1.1

• x1, x4, or x8 lane support per block

• Works in conjunction with RocketIO transceivers

• Tri-mode 10/100/1000 Mb/s Ethernet MACs

• RocketIO GTX transceivers can be used as PHY or connect to external PHY using many programmable Media 

Independent Interface (MII) options

• RocketIO GTX transceivers 150 Mb/s to 4.25 Gb/s

• 65 nm copper CMOS process technology

• 1.0V core voltage