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Lattice LFX125EB-04F256I STOCK

 ■ Non-volatile, Infinitely Reconfigurable

• Instant-on - Powers up in microseconds viaon-chip E2CMOS® based memory

• No external configuration memory

• Excellent design security, no bit stream to intercept

• Reconfigure SRAM based logic in milliseconds

■ High Logic Density for System-levelIntegration

• 139K to 1.25M system gates

• 160 to 496 I/O

• 1.8V, 2.5V, and 3.3V VCC operation

• Up to 414Kb sysMEM™ embedded memory

■ High Performance Programmable FunctionUnit (PFU)

• Four LUT-4 per PFU supports wide and narrowfunctions

• Dual flip-flops per LUT-4 for extensive pipelining

• Dedicated logic for adders, multipliers, multiplexers, and counters

■ Flexible Memory Resources

• Multiple sysMEM Embedded RAM Blocks– Single port, Dual port, and FIFO operation

• 64-bit distributed memory in each PFU– Single port, Double port, FIFO, and ShiftRegister operation

■ Flexible Programming, Reconfiguration,and Testing

• Supports IEEE 1532 and 1149.1

• Microprocessor configuration interface

• Program E2CMOS while operating from SRAM

■ Eight sysCLOCK™ Phase Locked Loops(PLLs) for Clock Management

• True PLL technology

• 10MHz to 320MHz operation

• Clock multiplication and division

• Phase adjustment

• Shift clocks in 250ps steps

■ sysIO™ for High System Performance

• High speed memory support through SSTL andHSTL

• Advanced buses supported through PCI, GTL+,LVDS, BLVDS, and LVPECL

• Standard logic supported through LVTTL,LVCMOS 3.3, 2.5 and 1.8

• 5V tolerant I/O for LVCMOS 3.3 and LVTTLinterfaces

• Programmable drive strength for series termination

• Programmable bus maintenance

■ Two Options Available

• High-performance sysHSI (standard part number)

• Low-cost, no sysHSI (“E-Series”)

■ sysHSI™ Capability for Ultra Fast SerialCommunications

• Up to 800Mbps performance

• Up to 20 channels per device

• Built in Clock Data Recovery (CDR) andSerialization and De-serialization (SERDES)


How to Order

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