General description:

The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and3-state outputs. Both the shift and storage register have separate clocks. The device features aserial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MRinput. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitionsof the SHCP input. The data in the shift register is transferred to the storage register on aLOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift registerwill always be one clock pulse ahead of the storage register. Data in the storage register appearsat the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputsto assume a high-impedance OFF-state. Operation of the OE input does not affect the state ofthe registers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the useof these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at allinputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified forpartial power down applications using IOFF. The IOFF circuitry disables the output, preventing thepotentially damaging backflow current through the device when it is powered down.

Features and benefits:

• Wide supply voltage range from 1.2 V to 3.6 V

• Overvoltage tolerant inputs to 5.5 V

• CMOS low power dissipation

• Direct interface with TTL levels

• IOFF circuitry provides partial Power-down mode operation

• Balanced propagation delays

• All inputs have Schmitt-trigger action

• Complies with JEDEC standard:

• JESD8-7A (1.65 V to 1.95 V)

• JESD8-5A (2.3 V to 2.7 V)

• JESD8-C/JESD36 (2.7 V to 3.6 V)

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications:

• Serial-to-parallel data conversion

• Remote control holding register