General description：

The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers forembedded applications featuring a high level of integration and low power consumption.The Arm Cortex-M3 is a next generation core that offers system enhancements such asenhanced debug features and a higher level of support block integration.The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. TheLPC1769 operates at CPU frequencies of up to 120 MHz. The Arm Cortex-M3 CPUincorporates a 3-stage pipeline and uses a Harvard architecture with separate localinstruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPUalso includes an internal prefetch unit that supports speculative branching.The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB offlash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTGinterface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSPcontrollers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface,8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface,four general purpose timers, 6-output general purpose PWM, ultra-low power Real-TimeClock (RTC) with separate battery supply, and up to 70 general purpose I/O pins.The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x Arm7-basedmicrocontroller series.For additional documentation, see Section 19 “References”.

Features and benefits：

 Arm Cortex-M3 processor, running at frequencies of up to 100 MHz(LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit(MPU) supporting eight regions is included.

 Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Up to 512 kB on-chip flash programming memory. Enhanced flash memory acceleratorenables high-speed 120 MHz operation with zero wait states.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chipbootloader software.

 On-chip SRAM includes:

 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPUaccess.

 Two/one 16 kB SRAM blocks with separate access paths for higher throughput.These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well asfor general purpose CPU instruction and data storage.

 Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayermatrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital andDigital-to-Analog converter peripherals, timer match signals, and formemory-to-memory transfers.

 Multilayer AHB matrix interconnect provides a separate bus for each AHB master.AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, andthe USB interface. This interconnect provides communication with no arbitrationdelays.

 Split APB bus allows high throughput with few stalls between the CPU and DMA.

 Serial interfaces:

 Ethernet MAC with RMII interface and dedicated DMA controller. (Not available onall parts, see Table 2.)

 USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller andon-chip PHY for device, Host, and OTG functions. (Not available on all parts, seeTable 2.)

 Four UARTs with fractional baud rate generation, internal FIFO, and DMA support.One UART has modem control I/O and RS-485/EIA-485 support, and one UARThas IrDA support.

 CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.)

 SPI controller with synchronous, serial, full duplex communication andprogrammable data length.

 Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfacescan be used with the GPDMA controller.

 Three enhanced I2C bus interfaces, one with an open-drain output supporting fullI2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standardport pins. Enhancements include multiple address recognition and monitor mode.

 I2S (Inter-IC Sound) interface for digital audio input or output, with fractional ratecontrol. The I2S-bus interface can be used with the GPDMA. The I2S-bus interfacesupports 3-wire and 4-wire data transmit and receive as well as master clockinput/output. (Not available on all parts, see Table 2.)

 Other peripherals:

 70 (100 pin package) General Purpose I/O (GPIO) pins with configurablepull-up/down resistors. All GPIOs support a new, configurable open-drain operatingmode. The GPIO block is accessed through the AHB multilayer bus for fast accessand located in memory such that it supports Cortex-M3 bit banding and use by theGeneral Purpose DMA Controller.

 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC canbe used with the GPDMA controller.

 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMAsupport. (Not available on all parts, see Table 2)

 Four general purpose timers/counters, with a total of eight capture inputs and tencompare outputs. Each timer block has an external count input. Specific timerevents can be selected to generate DMA requests.

 One motor control PWM with support for three-phase motor control.

 Quadrature encoder interface that can monitor one external quadrature encoder.

 One standard PWM/timer block with external count input.

 RTC with a separate power domain and dedicated RTC oscillator. The RTC blockincludes 20 bytes of battery-powered backup registers.

 WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,the RTC oscillator, or the APB clock.

 Arm Cortex-M3 system tick timer, including an external clock input option.

 Repetitive interrupt timer provides programmable and repeating timed interrupts.

 Each peripheral has its own clock divider for further power savings.

 Standard JTAG debug interface for compatibility with existing tools. Serial Wire Debugand Serial Wire Trace Port options. Boundary Scan Description Language (BSDL) isnot available for this device.

 Emulation trace module enables non-intrusive, high-speed real-time tracing ofinstruction execution.

 Integrated PMU (Power Management Unit) automatically adjusts internal regulators tominimize power consumption during Sleep, Deep sleep, Power-down, and Deeppower-down modes.

 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.

 Single 3.3 V power supply (2.4 V to 3.6 V).

 Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0and Port 2 can be used as edge sensitive interrupt sources.

 Non-maskable Interrupt (NMI) input.

 Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,CPU clock, and the USB clock.

 The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up fromany priority interrupt that can occur while the clocks are stopped in deep sleep,Power-down, and Deep power-down modes.

 Processor wake-up from Power-down mode via any interrupt able to operate duringPower-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernetwake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI).

 Brownout detect with separate threshold for interrupt and forced reset.

 Power-On Reset (POR).

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as asystem clock.

 PLL allows CPU operation up to the maximum CPU rate without the need for ahigh-frequency crystal. May be run from the main oscillator, the internal RC oscillator,or the RTC oscillator.

 USB PLL for added flexibility.

 Code Read Protection (CRP) with different security levels.

 Unique device serial number for identification purposes.

 Available as LQFP100 (14 mm  14 mm  1.4 mm), TFBGA1001 (9 mm  9 mm  0.7mm), and WLCSP100 (5.07  5.07  0.53 mm) package.

Applications：

 eMetering 

 Alarm systems

 Lighting 

 White goods

 Industrial networking 

 Motor control