FeaturesNotes:

•VDD = VDDQ = 1.2V ±60mV

•VPP=2.5V,-125mV,+250mV•On-die, internal, adjustable VREFDQ generations 

•1.2V pseudo open-drain I/Os 

•TC maximum up to 95℃

- 64ms, 8192-cycle refresh up to 85℃

-32ms, 8192-cycle refresh at >85℃ to 95℃ 

•16 internal banks (x4, x8): 4 groups of 4 banks eachs 

• 8 internal banks (x16): 2 groups of 4 banks eachs 

• 8n-bit prefetch architectures 

• Programmable data strobe preambless 

• Data strobe preamble trainings 

• Command/Address latency (CAL)s 

• Multipurpose register READ and WRITE capabilitys 

• Write levelings 

• Self refresh modes 

• Low-power auto self refresh (LPASR)s 

•Temperature controlled refresh (TCR)s 

• Fine granularity refreshs 

• Self refresh aborts 

• Maximum power savings 

• Output driver calibrations 

• Nominal, park, and dynamic on-die termination(ODT)s 

• Data bus inversion (DBI) for data buss 

• Command/Address (CA) paritys 

• Databus write cyclic redundancy check (CRC)s 

• Per-DRAM addressability

• Connectivity tests 

• JEDEC JESD-79-4 compliants 

• sPPR and hPPR capabilitys 

• MBIST-PPR support (Die Revision F