General description:

The P82B715 is a bipolar IC intended for application in I2C-bus and derivative bussystems. While retaining all the operating modes and features of the I2C-bus it permitsextension of the practical separation distance between components on the I2C-bus bybuffering both the data (SDA) and the clock (SCL) lines.The I2C-bus capacitance limit of 400 pF restricts practical communication distances to afew meters. Using one P82B715 at each end of a long cable (connecting Lx/Ly to Lx/Ly)reduces that cable’s loading on the linked I2C-buses by a factor of 10 and allows the totalsystem capacitance load (all devices, cable, connectors, and traces or wires connected tothe I2C-bus) to be around 3000 pF while the loading on each I2C-bus on the Sx/Sy sidesremains below 400 pF. Longer cables or low-cost, general-purpose wiring may be used tolink I2C-bus based modules without degrading noise margins. Multiple P82B715s can beconnected together, linking their Lx/Ly ports, in a star or multi-point architecture as long asthe total capacitance of the system is less than about 3000 pF and each bus at an Sx/Syconnection is well below 400 pF. This configuration, with the master and/or slave devicesattached to the Sx/Sy port of each P82B715, has full multi-master communicationcapability. The P82B715 alone does not support voltage level translation, but it can besimply implemented using low cost transistors when required. There is no restriction oninterconnecting the Sx/Sy I/Os, and, because the device output levels are always heldwithin 100 mV of input drive levels, P82B715 is compatible with bus buffers that usevoltage level offsets, e.g., PCA9511A, PCA9517, Sx/Sy side of P82B96.The lower VOL level and ability to operate with any master, slave or bus buffer is theprimary advantage of the using the P82B715 for long distance buses at the disadvantageof not isolating bus capacitance like the P82B96 or PCA9600 are able to do. The primarydisadvantage of the P82B96 and PCA9600 is that the static level offset needed to isolatebus capacitance does not allow these devices to operate with other bus buffers withspecial offset levels or with master/slaves that require a VIL lower than 0.8 V with noisemargin. A proven quick design-in point-to-point/multi-point circuit (Figure 9) is included inSection 8.2 to allow rapid use of the P82B715 along with comparison waveforms so thatthe designer can clearly see the trade-offs between the P82B715 and theP82B96/PCA9600 and choose the type of device that is best for their application.

 Features:

■ Dual, bidirectional, unity voltage gain buffer with no external directional controlrequired

■ Compatible with I2C-bus and its derivatives SMBus, PMBus, DDC, etc.

■ Logic signal levels may include (but not exceed) both supply and ground

■ Logic signal input voltage levels are output without change and are independent of VCC

■ ×10 impedance transformation, but does not change logic voltage levels

■ Supply voltage range 3 V to 12 V

■ Clock speeds to at least 100 kHz and 400 kHz when other system delays permit

■ ESD protection exceeds 2500 V HBM per Mil. Std 883C-3015.7 and 400 V MM perJESD22-A115 (I/Os have diodes to VCC and GND)

■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Applications:

■ Increase the total connected capacitance of an I2C-bus system to around 3000 pF

■ Drive I2C-bus signals over long cables to approximately 50 meters or 3000 pF

■ Drives ×10 lower impedance bus wiring for improved noise immunity

■ Multi-drop distribution of I2C-bus signals using low cost twisted-pair cables

■ AdvancedTCA radial IPMB architecture

■ Driving 30 mA Fm+ devices from standard 3 mA parts