GENERAL DESCRIPTION:

The AD9364 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G basestation applications. Its programmability and wideband capabilitymake it ideal for a broad range of transceiver applications.The device combines an RF front end with a flexible mixed-signalbaseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to aprocessor. The AD9364 operates in the 70 MHz to 6.0 GHz range,covering most licensed and unlicensed bands. Channel bandwidthsfrom less than 200 kHz to 56 MHz are supported.The direct conversion receiver has state-of-the-art noise figureand linearity. The receive (Rx) subsystem includes independentautomatic gain control (AGC), dc offset correction, quadraturecorrection, and digital filtering, thereby eliminating the need forthese functions in the digital baseband. The AD9364 also hasflexible manual gain modes that can be externally controlled.Two high dynamic range ADCs digitize the received I and Qsignals and pass them through configurable decimation filters and 128-tap FIR filters to produce a 12-bit output signal at theappropriate sample rate.

The transmitter uses a direct conversion architecture that achieveshigh modulation accuracy with ultralow noise. This transmitterdesign produces a Tx EVM of ≤−40 dB, allowing significant systemmargin for the external power amplifier (PA) selection. The onboard transmit (Tx) power monitor can be used as a powerdetector, enabling highly accurate Tx power measurements.The fully integrated phase-locked loops (PLLs) provide lowpower fractional-N frequency synthesis for all Rx and Tx channels.All VCO and loop filter components are integrated.The core of the AD9364 can be powered directly from a 1.3 Vregulator. The IC is controlled via a standard 4-wire serial port andfour real-time input control pins. Comprehensive power-downmodes are included to minimize power consumption duringnormal use. The AD9364 is packaged in a 10 mm × 10 mm,144-ball chip scale package ball grid array (CSP_BGA). 

FEATURESRF:

 1 × 1 transceiver with integrated 12-bit DACs and ADCsBand: 70 MHz to 6.0 GHzSupports time division duplex (TDD) and frequency divisionduplex (FDD) operationTunable channel bandwidth (BW): <200 kHz to 56 MHz3-band receiver: 3 differential or 6 single-ended inputsSuperior receiver sensitivity with a noise figure of <2.5 dBRx gain controlReal-time monitor and control signals for manual gainIndependent automatic gain control2-band differential output transmitterHighly linear broadband transmitterTx EVM: ≤−40 dBTx noise: ≤−157 dBm/Hz noise floorTx monitor: ≥66 dB dynamic range with 1 dB accuracyIntegrated fractional-N synthesizers2.4 Hz maximum local oscillator (LO) step sizeMultichip synchronizationCMOS/LVDS digital interface

APPLICATIONS:

Point to point communication systems

Femtocell/picocell/microcell base stations

General-purpose radio systems