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Winbond W9825G6KH-6 Datesheet

The W9825G6KH is a high-speed synchronous dynamic random access memory (SDRAM) organized as 4M words × 4 banks × 16 bits, delivering a data bandwidth of up to 200 million words per second. The W9825G6KH-6 grade is compliant with the 166MHz/CL3 specification. Access to the SDRAM is burst-oriented, supporting burst lengths of 1, 2, 4, 8, or full page. The device features programmable Mode Register for burst length, CAS latency (2 or 3), and burst type (interleaved or sequential), allowing system performance optimization. Multiple internal banks enable interleaving to hide precharging time. The device supports self refresh mode (including low power option on certain grades), power down mode, auto-precharge, byte data control via LDQM/UDQM, and operates with an LVTTL interface. Housed in a TSOP II 54-pin, 400 mil, 0.80mm pitch package, the W9825G6KH is RoHS compliant and lead-free. It is ideal for main memory in high-performance applications requiring 3.3V operation.

GENERAL DESCRIPTION:

W9825G6KH is a high-speed synchronous dynamic random access memory (SDRAM), organized as4M words  4 banks  16 bits. W9825G6KH delivers a data bandwidth of up to 200M words persecond. To fully comply with the personal computer industrial standard, W9825G6KH is sorted into thefollowing speed grades: -5, -5I, -6, -6I, -6L, -75 and 75L. The -5/-5I grade parts are compliant to the200MHz/CL3 specification (the -5I industrial grade which is guaranteed to support -40°C ≤ TA ≤ 85°C).The -6/-6I/-6L grade parts are compliant to the 166MHz/CL3 specification (the -6I industrial gradewhich is guaranteed to support -40°C ≤ TA ≤ 85°C). The -75/75L is compliant to the 133MHz/CL3specification. The -6L and 75L parts support self refresh current IDD6 max. 1.5 mA.Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can beaccessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVEcommand. Column addresses are automatically generated by the SDRAM internal counter in burstoperation. Random column read is also possible by providing its address at each clock cycle. Themultiple bank nature enables interleaving among internal banks to hide the precharging time.By having a programmable Mode Register, the system can change burst length, latency cycle,interleave or sequential burst to maximize its performance. W9825G6KH is ideal for main memory inhigh performance applications.


FEATURES:

 3.3V ± 0.3V Power Supply

 Up to 200 MHz Clock Frequency

 4,194,304 Words  4 Banks  16 Bits Organization

 Self Refresh Mode: Standard and Low Power

 CAS Latency: 2 and 3

 Burst Length: 1, 2, 4, 8 and Full Page

 Burst Read, Single Writes Mode

 Byte Data Controlled by LDQM, UDQM

 Power Down Mode

 Auto-precharge and Controlled Precharge

 8K Refresh Cycles/64 mS

 Interface: LVTTL

 Packaged in TSOP II 54-pin, 400 mil - 0.80, using Lead free materials with RoHS compliant



 


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