Features:
⚫ Basis LPDDR3 Compliant
- Low Power Consumption
- 8n Prefetch Architecture and BL8 only
⚫ Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination1
- ZQ Calibration for DS/ODT impedance accuracy viaexternal ZQ pad (240Ω± 1%)
⚫ Training for Signals’ Synchronization
- DQ Calibration offering specific DQ output patterns
- CA Training
- Write Leveling via MR settings 2
⚫ Data Integrity
- DRAM built-in Temperature Sensor forTemperature Compensated Self Refresh (TCSR)
- Auto Refresh and Self Refresh Modes
⚫ Power Saving Modes
- Deep Power Down Mode (DPD)
- Partial Array Self Refresh (PASR)
- Clock Stop capability during idle period
⚫ HSUL12 interface and Power Supply
- VDD1= 1.70 to 1.95V- VDD2/VDDQ/VDDCA = 1.14 to 1.3V
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