Features:

This data sheet specifies the operation of the unifiedLPDDR4 and LPDDR4X product, and first describesspecific requirements for LPDDR4X 0.6V VDDQoperation. When using the product as an LPDDR4device, refer to LPDDR4 setting section LPDDR4 1.10VVDDQ at the end of this data sheet.• Ultra-low-voltage core and I/O power supplies

- VDD1 = 1.70–1.95V; 1.80V nominal

- VDD2 = 1.06–1.17V; 1.10V nominal

- VDDQ = 0.57–0.65V; 0.60V nominalor VDDQ = 1.06–1.17V; 1.10V nomina

l• Frequency range- 2133–10 MHz (data rate range per pin: 4266–20Mb/s)

• 16n prefetch DDR architecture

• 8 internal banks per channel for concurrentoperation

• Single-data-rate CMD/ADR entry

• Bidirectional/differential data strobe per byte lane

• Programmable READ and WRITE latencies (RL/WL)

• Programmable and on-the-fly burst lengths (BL =16, 32)

• Directed per-bank refresh for concurrent bankoperation and ease of command scheduling

• Up to 8.5 GB/s per die x32 channel

• On-chip temperature sensor to control self refreshrate

• Partial-array self refresh (PASR)

• Selectable output drive strength (DS)

• Clock-stop capability

• RoHS-compliant, “green” packaging

• Programmable VSS (ODT) termination

• Single-ended CK and DQS support