Features：

 Data Integrity

- Auto Self Refresh (ASR) by DRAM built-in TS

- Auto Refresh and Self Refresh Modes

 DRAM Access Bandwidth

- Separated IO gating structures by Bank Groups

- Self Refresh Abort

- Fine Granularity Refresh

 Signal Synchronization

- Write Leveling via MR settings1

- Read Leveling via MPR

 Reliability & Error Handling

- Command/Address Parity

- Databus Write CRC

- MPR readout

- Boundary Scan (X16)

- Post Package Repair

 Signal Integrity

- Internal VREFDQ Training

- Read Preamble Training

- Gear Down Mode

- Per DRAM Addressability

- Configurable DS for system compatibility

- Configurable On-Die Termination- Data bus inversion (DBI)

- ZQ Calibration for DS/ODT impedance accuracyvia external ZQ pad (240 Ω ± 1%)

 Power Saving & Efficiency

- POD with VDDQ termination

- Command/Address Latency (CAL)

- Maximum Power Saving

- Low-power Auto Self Refresh (LPASR)

Programmable Functions：

 Output Driver Impedance (34/48)

 CAS Write Latency (9/10/11/12/14/16/18/20)

 Additive Latency (0/CL-1/CL-2)

  to Command Address Latency (3/4/5/6/8)

 Command Address Parity Latency (4/5/6)

 Write Recovery Time (10/12/14/16/18/20/24)

 Burst Type (Sequential/Interleaved)

 RTT_PARK (34/40/48/60/80/120/240)

 RTT_NOM (34/40/48/60/80/120/240)

 RTT_WR (80/120/240)

 Read Preamble (1T/2T)

 Write Preamble (1T/2T)

 Burst Length (BL8/BC4/BC4 or 8 on the fly)

 LPASR (Manual: Normal/Reduced/Extended, Auto:TS)