GENERAL DESCRIPTION:

The NM1820 series 32-bit microcontroller(MCU) is embedded with ARM® Cortex™-M0 core andmonolithic half-bridge gate driver for motor driver applications which require high performance,high integration, and low cost. The Cortex™-M0 is the newest ARM®embedded processor with32-bit performance at a cost equivalent to the traditional 8-bit microcontroller.The MCU of NM1820 series can run up to 48 MHz and offers 17.5K-bytes embedded programflash, size configurable data flash (shared with program flash), 2K-byte flash for the ISP, and 2Kbyte SRAM. Many system level peripheral functions, such as I/O Port, Timer, UART, SPI, I2C,ADC, Watchdog Timer, Analog Comparator and Brown-out Detector, have been incorporated intothe NM1820 series in order to reduce component count, board space and system cost. Theseuseful functions make the NM1820 series powerful for a wide range of motor driver applications.The power supply input of NM1820 is up to 40V. The UVLO circuits prevent malfunction whenVCC is lower than the specified threshold voltage. It also build-in bootstrap diodes that canreduce output component.Additionally, the NM1820 series is equipped with ISP (In-System Programming) and ICP (InCircuit Programming) functions, which allow the user to update the program memory withoutremoving the chip from the actual end product.

FEATURES:

 Operation Supply Voltage VIN Range from 4.5 to 30V

 Gate Driver (half-bridge gate drive)

 3 low-side and 3 high-side gate drivers

 More than 0.6A gate driving capability

 UVLO(Under voltage lockout=4.1V) function to disable PWM output (PWMoutput low)

 Embedded two Internal 5V voltage regulators with 35mA driving capability

 Matched propagation delay of around 500ns for both PWM complementarychannels

 PWM output delay matching < 50 ns

 Max VGS of Power MOS is up to 5V

 Thermal shutdown circuitry to limit the junction temperature at 125 ℃

 MCU Core

 ARM® Cortex™-M0 core running up to 48 MHz

 One 24-bit system timer

 Supports Low Power Sleep mode

 A single-cycle 32-bit hardware multiplier

 NVIC for the 32 interrupt inputs, each with 4-level of priority

 Supports Serial Wire Debug (SWD) interface and two watch points/fourbreakpoints

 Hardware Divider

 Signed (two’s complement) integer calculation

 32-bit dividend with 16-bit divisor calculation capacity

 32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extendsto 32-bit)

 Divided by zero warning flag

 6 HCLK clocks taken for one cycle calculation

 Waiting for calculation ready automatically when reading quotient and remainder

 Memory

 17.5 KB Flash memory for program memory (APROM)

 Configurable Flash memory for data memory (Data Flash)

 2 KB Flash for loader (LDROM)

 2 KB SRAM for internal scratch-pad RAM (SRAM)

 Clock Control

 48 MHz internal oscillator (HIRC) (±1% accuracy at 25OC, 5V)

 Dynamically calibrating the HIRC OSC to 48 MHz ±2% from -40OC to 105OCby external 32.768K crystal oscillator (LXT)

 10 kHz internal low-power oscillator (LIRC) for Watchdog Timer and Powerdown wake-up

 Timer

 Supports external capture pin (T1EX) for interval measurement

 Support advanced capture function(P3.0) can continuous capture 4 edge on onesignal

 Provides two channel 32-bit timers. One 8-bit pre-scale counter with 24-bit upcounter for each timer

 Independent clock source for each timer

 Provides One-shot, Periodic, Toggle and Continuous operation modes

 24-bit up counter value is readable through TDR (Timer Data Register)

 Provides trigger counting/free counting/counter reset function triggered byexternal capture pin or internal comparator signal

 Provides event counter function

 Supports wake-up from Idle or Power-down mode

 PWM

 Independent 16-bit PWM duty control units with maximum six outputs

 Supports group/synchronous/independent/ complementary modes

 Supports One-shot or Auto-reload mode

 Supports Edge-aligned and Center-aligned type

 Support Asymmetric mode

 Programmable dead-zone insertion between complementary channels

 Each output has independent polarity setting control

 Hardware fault brake and software brake protections

 Supports rising, falling, central, period, and fault break interrupts

 Supports duty/period trigger ADC conversion

 Timer comparing matching event trigger PWM to do phase change

 Supports comparator event trigger PWM to force PWM output low for currentperiod

 Provides interrupt accumulation function

 Gate driver PWM output by MCU PWM control