General Description：

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4bits. Each of the x8’s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columnsby 16 bits.Read and write accesses to the SDRAM are burst-oriented; accesses start at a selectedlocation and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with theACTIVE command are used to select the bank and row to be accessed (BA[1:0] select thebank; A[12:0] select the row). The address bits registered coincident with the READ orWRITE command are used to select the starting column location for the burst access.The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8locations, or the full page, with a burst terminate option. An auto precharge functionmay be enabled to provide a self-timed row precharge that is initiated at the end of theburst sequence.The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but italso allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the otherthree banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refreshmode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.SDRAMs offer substantial advances in DRAM operating performance, including theability to synchronously burst data at a high data rate with automatic column-addressgeneration, the ability to interleave between internal banks to hide precharge time, andthe capability to randomly change column addresses on each clock cycle during a burstaccess.

Features：

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positiveedge of system clock

• Internal, pipelined operation; column address canbe changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto prechargeand auto refresh modes

• Self refresh mode (not available on AT devices)

• Auto refresh

– 64ms, 8192-cycle refresh (commercial andindustrial)

– 16ms, 8192-cycle refresh (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply