Description：

This single positive-edge-triggered D-type flip-flop operates from 1.65V to 5.5V VCC. The NanoFree™ package technology represents a major breakthrough in IC packaging, utilizing the silicon die as the package. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the output regardless of the logic levels at the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the output on the positive edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the rise time of the clock pulse. After the hold time interval has elapsed, data at the D input can be changed without affecting the output levels. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Features：

Available in Texas Instruments' NanoFree™ package

Supports 5V VCC operation

Input voltage up to 5.5V

Maximum tpd of 5.9ns at 3.3V

Low power consumption with ICC maximum of 10µA

Output drive of ±24mA at 3.3V

VOLP (output ground bounce) typically less than 0.8V (VCC = 3.3V, TA = 25°C)

VOHV (output VOH undershoot) typically greater than 2V (VCC = 3.3V, TA = 25°C)

Ioff supports live insertion, partial-power-down mode, and back-drive protection

Latch-up performance exceeds 100mA per JESD 78 Class II

ESD protection exceeds JESD 22 specifications:

– 2000V Human-Body Model (HBM)

– 200V Machine Model (MM)

– 1000V Charged-Device Model (CDM)

Applications：

Servers

LED displays

Network switches

Telecommunications infrastructure

Motor drivers

I/O expanders