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Nanya NT5CC128M16JR-EK STOCK

The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation. It isinternally configured as an eight bank DRAMs.The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. Thesesynchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for generalapplications.The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and addressinputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS ordifferential DQS pair in a source synchronous fashion.These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available inBGA packages.

Descriptions:

The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation. It isinternally configured as an eight bank DRAMs.The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. Thesesynchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for generalapplications.The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and addressinputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS ordifferential DQS pair in a source synchronous fashion.These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available inBGA packages.

Features:

 JEDEC DDR3 Compliant

- 8n Prefetch Architecture

- Differential Clock(CK/) and Data Strobe(DQS/)

- Double-data rate on DQs, DQS and DM

 Data Integrity

- Auto Self Refresh (ASR) by DRAM built-in TS

- Auto Refresh and Self Refresh Modes

 Power Saving Mode

- Power Down Mode

 Signal Integrity

- Configurable DS for system compatibility

- Configurable On-Die Termination

- ZQ Calibration for DS/ODT impedance accuracy viaexternal ZQ pad (240 ohm ± 1%)

 Signal Synchronization

- Write Leveling via MR settings 5

- Read Leveling via MPR

 Interface and Power Supply

- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)

- SSTL_1353for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)

Options:

 Speed Grade (CL-TRCD-TRP) 1- 2133 Mbps / 14-14-14- 1866 Mbps / 13-13-13- 1600 Mbps / 11-11-11

 Temperature Range (Tc) 3- Commercial Grade = 0℃~95℃- Quasi Industrial Grade (-T) = -40℃~95℃- Industrial Grade (-I) = -40℃~95℃

Programmable Functions:

 CAS Latency (6/7/8/9/10/11/13/14)

 CAS Write Latency (5/6/7/8/9/10)

 Additive Latency (0/CL-1/CL-2)

 Write Recovery Time (5/6/7/8/10/12/14/16)

 Burst Type (Sequential/Interleaved)

 Burst Length (BL8/BC4/BC4 or 8 on the fly)

 Self RefreshTemperature Range(Normal/Extended)

 Output Driver Impedance (34/40)

 On-Die Termination of Rtt_Nom(20/30/40/60/120)

 On-Die Termination of Rtt_WR(60/120)

 Precharge Power Down (slow/fast)


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